There is a constant demand for increasing data storage capacity in digital systems. This results in continuous development of different ways to increase the density of magnetic recording. One of the recently developed, promising architectures of data storage systems, based on magnetic recording, is perpendicular recording, which is believed to have more high density potential compared to existing longitudinal recording. In longitudinal recording the magnetic medium on a disk is magnetized in a direction parallel to the surface of the disk, whereas in perpendicular recording, the media is magnetized in a direction perpendicular to the surface of the disk.
The nature of perpendicular recording brings its own difficulties. One difficulty is due to the fact that in longitudinal recording read-back signal has no DC component, while a significant part of perpendicular read-back signal power is located in low frequency region, a detrimental effect. In conventional read channel preamplifiers, capacitance coupling is used along the signal path, resulting in loss of any read-back signal DC component.
Another difficulty with perpendicular recording is linked to interference noise from neighboring tracks. For adjacent track-induced interference, suppression is usually effected by a high pass filter (HPF) with a steep loss at low frequencies. However, such a high pass filter eliminates not only the noise from adjacent tracks, but significant low frequency components of the read-back signal as well. As a consequence of the latter, a considerable amount of information in the written data is lost. The loss of the DC component also causes baseline “wander” in a read-back signal and makes initial data recovery difficult or impossible.
A block-diagram of a conventional PRML receiver for read-back signal processing is shown in FIG. 1. The receiver consists of read channel preamplifiers 100, analog low pass filter (LPF) 101, analog to digital converter (ADC) 102, high pass filter (HPF) 103, equalizer 104, clock recovery 105 and Viterbi decoder 106. The main function of HPF 103 is to mask the effects of sources of DC component loss and suppress low frequency noise, particularly, the noise that is caused by interference from adjacent tracks.
A block-diagram of a prior art Viterbi decoder is shown in FIG. 2. The Viterbi decoder of FIG. 2 constitutes a state machine, that comprises, in general case, N states. The Viterbi decoder includes a set of 2N metric calculators 200-0 . . . 200-(2N−1). In each metric calculator an expected ideal sample for the associated state and the hypothetical next bit is specified. At each sample interval, a metric calculator computes an Euclidean error metric as squared difference between the actual signal sample at Viterbi decoder input and an expected ideal sample. The computed metric is transferred from metric calculator to an associated one of the add-compare-select (ACS) circuits 201-0 . . . 201-(N−1). The ACS circuit adds the new computed metric to the previously accumulated branch metric for each of the two branches entering the corresponding state in the state transition diagram. Then, the two accumulated branch metrics compared, and the smaller is selected as the surviving branch metric for that state. For each state the Viterbi decoder finds a string of bits that provides the best approximation to the input signal on condition that this state survives. These strings of bits form candidates for future bits at the output of the Viterbi decoder and are kept in the candidate registers 203-0 . . . 203-(N−1). Each candidate register has a bidirectional exchange inout, that enables reading of the current contents of the candidate register and/or writing new contents into it. All bidirectional exchange inouts of the candidate registers 203-0 . . . 203-(N−1) are united. providing for a possible transfer of stored bits from one candidate register to another. Outputs of ACS circuits 201-0 . . . 201-(N−1) are connected to the inputs of candidate registers controller 202. In response to applied branch select control signals, the candidate registers controller 202 shifts into each of the candidate registers 203-0 . . . 203-(N−1) the appropriate binary symbol corresponding to the branch selected. Further, the candidate registers controller 202 merges the survivor candidate sequences, stored in candidate registers 203-0 . . . 203-(N−1) based on branches that were eliminated. Eventually all candidates merge into one survivor sequence, so that all candidates registers contain the same bits near their outputs. The Viterbi decoder output can be taken from the last cell of any one of the candidate registers; in FIG. 2 the output is taken from the last candidate register.
There are several different prior art methods of data detection in the presence of DC component loss. One of them, that is used more often than others, is disclosed in US Patent Application Serial No. 2003/0107831. According to this method, a feedback loop is added to the Viterbi decoder, as shown in FIG. 3. The feedback loop comprises two low pass filters: LPF1 302 and LPF2 303. Filter LPF1 302 complements the readback channel in the sense, that if the same digital signal is applied to the inputs of LPF1 and read channel, then LPF1 output waveform coincides or is close to the suppressed low frequency part of read channel output. In the same sense filter LPF2 303 complements the HPF 103, that constitutes a part of PRML receiver, shown in FIG. 1. Detected digital signal from the Viterbi decoder 106 output is applied to the input of the filter LPF1 302, and the output of LPF1 302 is connected to the input of the filter LPF2 303. The signal at the output of the filter LPF2 303 represents DC component (or, what is the same, low frequency part) of the Viterbi decoder output and is supposed to be close to DC component of the original digital signal, that was written to the disk. This signal is added in the adder 300 to the signal, coming to the Viterbi decoder input. Thus, the DC component restoration and corresponding improvement of the overall system performance are ensured.
This method of DC component restoration, while being somewhat effective, has however a serious drawback. The output signal of the Viterbi decoder of FIG. 2 is delayed in relation to the input signal for m bits, the delay m being equal to combined length of a candidate register 203-i and a state. Typically in the prior art, m lies in the range 10–20 bits. If length of a bit cell is T seconds, then time delay that occurs in the Viterbi decoder, equals mT seconds. The DC component of the Viterbi decoder output signal is delayed in relation to the input signal for the same interval of mT seconds. As a consequence, DC component restoration occurs with some distortions. As a result, a source of additional errors appears that is especially noticeable when bit error rate is low.
An algorithm, that provides for DC component restoration in data storage system, based on magnetic perpendicular recording, without unwanted delay between restored DC component and original read-back signal and that, therefore, avoids occurrence of additional errors, would be a significant improvement in the art.